Автор работы: Пользователь скрыл имя, 01 Декабря 2012 в 20:48, курсовая работа
IP-ядро является блоком логической схемы, которое используется в изготовлении программируемой матрицы логических элементов или специальных интегральных схем. Таким образом, IP-ядро является универсальным элементом при построении интегральных схем. Идеально, IP ядро должно быть полностью переносным – то есть легко устанавливаемым в любую технику. Универсальные асинхронные приемопередатчики, центральные процессоры, регуляторы (контроллеры) Ethernet, и интерфейсы PCI – все примеры ядер IP.
Календарный план
Аннотация
Введение
Техническое задание
Разработка VHDL модели проектируемого устройства
• Граф переходов состояний микропроцессора
• Синтез устройства
• Структурная схема устройства
• Текст программы на языке VHDL
RB3(1) <= RA3signal(1) AND RA3signal(1);
RB3(2) <= RA3signal(2) AND RA3signal(2);
RB3(3) <= RA3signal(3) AND RA3signal(3);
RB3(4) <= RA3signal(4) AND RA3signal(4);
RB3(5) <= RA3signal(5) AND RA3signal(5);
RB3(6) <= RA3signal(6) AND RA3signal(6);
RB3(7) <= RA3signal(7) AND RA3signal(7);
when "00111001" =>
RB3(0) <= RA4signal(0) AND RA3signal(0);
RB3(1) <= RA4signal(1) AND RA3signal(1);
RB3(2) <= RA4signal(2) AND RA3signal(2);
RB3(3) <= RA4signal(3) AND RA3signal(3);
RB3(4) <= RA4signal(4) AND RA3signal(4);
RB3(5) <= RA4signal(5) AND RA3signal(5);
RB3(6) <= RA4signal(6) AND RA3signal(6);
RB3(7) <= RA4signal(7) AND RA3signal(7);
when "00001101" =>
RB4(0) <= RA1signal(0) AND RA4signal(0);
RB4(1) <= RA1signal(1) AND RA4signal(1);
RB4(2) <= RA1signal(2) AND RA4signal(2);
RB4(3) <= RA1signal(3) AND RA4signal(3);
RB4(4) <= RA1signal(4) AND RA4signal(4);
RB4(5) <= RA1signal(5) AND RA4signal(5);
RB4(6) <= RA1signal(6) AND RA4signal(6);
RB4(7) <= RA1signal(7) AND RA4signal(7);
when "00011101" =>
RB4(0) <= RA2signal(0) AND RA4signal(0);
RB4(1) <= RA2signal(1) AND RA4signal(1);
RB4(2) <= RA2signal(2) AND RA4signal(2);
RB4(3) <= RA2signal(3) AND RA4signal(3);
RB4(4) <= RA2signal(4) AND RA4signal(4);
RB4(5) <= RA2signal(5) AND RA4signal(5);
RB4(6) <= RA2signal(6) AND RA4signal(6);
RB4(7) <= RA2signal(7) AND RA4signal(7);
when "00101101" =>
RB4(0) <= RA3signal(0) AND RA4signal(0);
RB4(1) <= RA3signal(1) AND RA4signal(1);
RB4(2) <= RA3signal(2) AND RA4signal(2);
RB4(3) <= RA3signal(3) AND RA4signal(3);
RB4(4) <= RA3signal(4) AND RA4signal(4);
RB4(5) <= RA3signal(5) AND RA4signal(5);
RB4(6) <= RA3signal(6) AND RA4signal(6);
RB4(7) <= RA3signal(7) AND RA4signal(7);
when "00111101" =>
RB4(0) <= RA4signal(0) AND RA4signal(0);
RB4(1) <= RA4signal(1) AND RA4signal(1);
RB4(2) <= RA4signal(2) AND RA4signal(2);
RB4(3) <= RA4signal(3) AND RA4signal(3);
RB4(4) <= RA4signal(4) AND RA4signal(4);
RB4(5) <= RA4signal(5) AND RA4signal(5);
RB4(6) <= RA4signal(6) AND RA4signal(6);
RB4(7) <= RA4signal(7) AND RA4signal(7);
------------------------------
when "00000011" =>
RB1(0) <= RA1signal(0) XOR RA1signal(0);
RB1(1) <= RA1signal(1) XOR RA1signal(1);
RB1(2) <= RA1signal(2) XOR RA1signal(2);
RB1(3) <= RA1signal(3) XOR RA1signal(3);
RB1(4) <= RA1signal(4) XOR RA1signal(4);
RB1(5) <= RA1signal(5) XOR RA1signal(5);
RB1(6) <= RA1signal(6) XOR RA1signal(6);
RB1(7) <= RA1signal(7) XOR RA1signal(7);
when "00010011" =>
RB1(0) <= RA2signal(0) XOR RA1signal(0);
RB1(1) <= RA2signal(1) XOR RA1signal(1);
RB1(2) <= RA2signal(2) XOR RA1signal(2);
RB1(3) <= RA2signal(3) XOR RA1signal(3);
RB1(4) <= RA2signal(4) XOR RA1signal(4);
RB1(5) <= RA2signal(5) XOR RA1signal(5);
RB1(6) <= RA2signal(6) XOR RA1signal(6);
RB1(7) <= RA2signal(7) XOR RA1signal(7);
when "00100011" =>
RB1(0) <= RA3signal(0) XOR RA1signal(0);
RB1(1) <= RA3signal(1) XOR RA1signal(1);
RB1(2) <= RA3signal(2) XOR RA1signal(2);
RB1(3) <= RA3signal(3) XOR RA1signal(3);
RB1(4) <= RA3signal(4) XOR RA1signal(4);
RB1(5) <= RA3signal(5) XOR RA1signal(5);
RB1(6) <= RA3signal(6) XOR RA1signal(6);
RB1(7) <= RA3signal(7) XOR RA1signal(7);
when "00110011" =>
RB1(0) <= RA4signal(0) XOR RA1signal(0);
RB1(1) <= RA4signal(1) XOR RA1signal(1);
RB1(2) <= RA4signal(2) XOR RA1signal(2);
RB1(3) <= RA4signal(3) XOR RA1signal(3);
RB1(4) <= RA4signal(4) XOR RA1signal(4);
RB1(5) <= RA4signal(5) XOR RA1signal(5);
RB1(6) <= RA4signal(6) XOR RA1signal(6);
RB1(7) <= RA4signal(7) XOR RA1signal(7);
when "00000111" =>
RB2(0) <= RA1signal(0) XOR RA2signal(0);
RB2(1) <= RA1signal(1) XOR RA2signal(1);
RB2(2) <= RA1signal(2) XOR RA2signal(2);
RB2(3) <= RA1signal(3) XOR RA2signal(3);
RB2(4) <= RA1signal(4) XOR RA2signal(4);
RB2(5) <= RA1signal(5) XOR RA2signal(5);
RB2(6) <= RA1signal(6) XOR RA2signal(6);
RB2(7) <= RA1signal(7) XOR RA2signal(7);
when "00010111" =>
RB2(0) <= RA2signal(0) XOR RA2signal(0);
RB2(1) <= RA2signal(1) XOR RA2signal(1);
RB2(2) <= RA2signal(2) XOR RA2signal(2);
RB2(3) <= RA2signal(3) XOR RA2signal(3);
RB2(4) <= RA2signal(4) XOR RA2signal(4);
RB2(5) <= RA2signal(5) XOR RA2signal(5);
RB2(6) <= RA2signal(6) XOR RA2signal(6);
RB2(7) <= RA2signal(7) XOR RA2signal(7);
when "00100111" =>
RB2(0) <= RA3signal(0) XOR RA2signal(0);
RB2(1) <= RA3signal(1) XOR RA2signal(1);
RB2(2) <= RA3signal(2) XOR RA2signal(2);
RB2(3) <= RA3signal(3) XOR RA2signal(3);
RB2(4) <= RA3signal(4) XOR RA2signal(4);
RB2(5) <= RA3signal(5) XOR RA2signal(5);
RB2(6) <= RA3signal(6) XOR RA2signal(6);
RB2(7) <= RA3signal(7) XOR RA2signal(7);
when "00110111" =>
RB2(0) <= RA4signal(0) XOR RA2signal(0);
RB2(1) <= RA4signal(1) XOR RA2signal(1);
RB2(2) <= RA4signal(2) XOR RA2signal(2);
RB2(3) <= RA4signal(3) XOR RA2signal(3);
RB2(4) <= RA4signal(4) XOR RA2signal(4);
RB2(5) <= RA4signal(5) XOR RA2signal(5);
RB2(6) <= RA4signal(6) XOR RA2signal(6);
RB2(7) <= RA4signal(7) XOR RA2signal(7);
when "00001011" =>
RB3(0) <= RA1signal(0) XOR RA3signal(0);
RB3(1) <= RA1signal(1) XOR RA3signal(1);
RB3(2) <= RA1signal(2) XOR RA3signal(2);
RB3(3) <= RA1signal(3) XOR RA3signal(3);
RB3(4) <= RA1signal(4) XOR RA3signal(4);
RB3(5) <= RA1signal(5) XOR RA3signal(5);
RB3(6) <= RA1signal(6) XOR RA3signal(6);
RB3(7) <= RA1signal(7) XOR RA3signal(7);
when "00011011" =>
RB3(0) <= RA2signal(0) XOR RA3signal(0);
RB3(1) <= RA2signal(1) XOR RA3signal(1);
RB3(2) <= RA2signal(2) XOR RA3signal(2);
RB3(3) <= RA2signal(3) XOR RA3signal(3);
RB3(4) <= RA2signal(4) XOR RA3signal(4);
RB3(5) <= RA2signal(5) XOR RA3signal(5);
RB3(6) <= RA2signal(6) XOR RA3signal(6);
RB3(7) <= RA2signal(7) XOR RA3signal(7);
when "00101011" =>
RB3(0) <= RA3signal(0) XOR RA3signal(0);
RB3(1) <= RA3signal(1) XOR RA3signal(1);
RB3(2) <= RA3signal(2) XOR RA3signal(2);
RB3(3) <= RA3signal(3) XOR RA3signal(3);
RB3(4) <= RA3signal(4) XOR RA3signal(4);
RB3(5) <= RA3signal(5) XOR RA3signal(5);
RB3(6) <= RA3signal(6) XOR RA3signal(6);
RB3(7) <= RA3signal(7) XOR RA3signal(7);
when "00111011" =>
RB3(0) <= RA4signal(0) XOR RA3signal(0);
RB3(1) <= RA4signal(1) XOR RA3signal(1);
RB3(2) <= RA4signal(2) XOR RA3signal(2);
RB3(3) <= RA4signal(3) XOR RA3signal(3);
RB3(4) <= RA4signal(4) XOR RA3signal(4);
RB3(5) <= RA4signal(5) XOR RA3signal(5);
RB3(6) <= RA4signal(6) XOR RA3signal(6);
RB3(7) <= RA4signal(7) XOR RA3signal(7);
when "00001111" =>
RB4(0) <= RA1signal(0) XOR RA4signal(0);
RB4(1) <= RA1signal(1) XOR RA4signal(1);
RB4(2) <= RA1signal(2) XOR RA4signal(2);
RB4(3) <= RA1signal(3) XOR RA4signal(3);
RB4(4) <= RA1signal(4) XOR RA4signal(4);
RB4(5) <= RA1signal(5) XOR RA4signal(5);
RB4(6) <= RA1signal(6) XOR RA4signal(6);
RB4(7) <= RA1signal(7) XOR RA4signal(7);
when "00011111" =>
RB4(0) <= RA2signal(0) XOR RA4signal(0);
RB4(1) <= RA2signal(1) XOR RA4signal(1);
RB4(2) <= RA2signal(2) XOR RA4signal(2);
RB4(3) <= RA2signal(3) XOR RA4signal(3);
RB4(4) <= RA2signal(4) XOR RA4signal(4);
RB4(5) <= RA2signal(5) XOR RA4signal(5);
RB4(6) <= RA2signal(6) XOR RA4signal(6);
RB4(7) <= RA2signal(7) XOR RA4signal(7);
when "00101111" =>
RB4(0) <= RA3signal(0) XOR RA4signal(0);
RB4(1) <= RA3signal(1) XOR RA4signal(1);
RB4(2) <= RA3signal(2) XOR RA4signal(2);
RB4(3) <= RA3signal(3) XOR RA4signal(3);
RB4(4) <= RA3signal(4) XOR RA4signal(4);
RB4(5) <= RA3signal(5) XOR RA4signal(5);
RB4(6) <= RA3signal(6) XOR RA4signal(6);
RB4(7) <= RA3signal(7) XOR RA4signal(7);
when "00111111" =>
RB4(0) <= RA4signal(0) XOR RA4signal(0);
RB4(1) <= RA4signal(1) XOR RA4signal(1);
RB4(2) <= RA4signal(2) XOR RA4signal(2);
RB4(3) <= RA4signal(3) XOR RA4signal(3);
RB4(4) <= RA4signal(4) XOR RA4signal(4);
RB4(5) <= RA4signal(5) XOR RA4signal(5);
RB4(6) <= RA4signal(6) XOR RA4signal(6);
RB4(7) <= RA4signal(7) XOR RA4signal(7);
------------------------------
when "00000000" => RB1(0 to 7) <= RA1signal(0 to 7);
when "00010000" => RB1(0 to 7) <= RA2signal(0 to 7);
when "00100000" => RB1(0 to 7) <= RA3signal(0 to 7);
when "00110000" => RB1(0 to 7) <= RA4signal(0 to 7);
when "00000100" => RB2(0 to 7) <= RA1signal(0 to 7);
when "00010100" => RB2(0 to 7) <= RA2signal(0 to 7);
when "00100100" => RB2(0 to 7) <= RA3signal(0 to 7);
when "00110100" => RB2(0 to 7) <= RA4signal(0 to 7);
when "00001000" => RB3(0 to 7) <= RA1signal(0 to 7);
when "00011000" => RB3(0 to 7) <= RA2signal(0 to 7);
when "00101000" => RB3(0 to 7) <= RA3signal(0 to 7);
when "00111000" => RB3(0 to 7) <= RA4signal(0 to 7);
when "00001100" => RB4(0 to 7) <= RA1signal(0 to 7);
when "00011100" => RB4(0 to 7) <= RA2signal(0 to 7);
when "00101100" => RB4(0 to 7) <= RA3signal(0 to 7);
when "00111100" => RB4(0 to 7) <= RA4signal(0 to 7);
------------------------------
------------------------------
------------------------------
------------------------------
------------------------------
when "00000000" =>
RB1(0) <= L1(0) OR L1(0);
RB1(1) <= L1(1) OR L1(1);
RB1(2) <= L1(2) OR L1(2);
RB1(3) <= L1(3) OR L1(3);
RB1(4) <= L1(4) OR L1(4);
RB1(5) <= L1(5) OR L1(5);
RB1(6) <= L1(6) OR L1(6);
RB1(7) <= L1(7) OR L1(7);
when "00010000" =>
RB1(0) <= L2(0) OR L1(0);
RB1(1) <= L2(1) OR L1(1);
RB1(2) <= L2(2) OR L1(2);
RB1(3) <= L2(3) OR L1(3);
RB1(4) <= L2(4) OR L1(4);
RB1(5) <= L2(5) OR L1(5);
RB1(6) <= L2(6) OR L1(6);
RB1(7) <= L2(7) OR L1(7);
when "00100000" =>
RB1(0) <= L3(0) OR L1(0);
RB1(1) <= L3(1) OR L1(1);
RB1(2) <= L3(2) OR L1(2);
RB1(3) <= L3(3) OR L1(3);
RB1(4) <= L3(4) OR L1(4);
RB1(5) <= L3(5) OR L1(5);
RB1(6) <= L3(6) OR L1(6);
RB1(7) <= L3(7) OR L1(7);
when "00110000" =>
RB1(0) <= L4(0) OR L1(0);
RB1(1) <= L4(1) OR L1(1);
RB1(2) <= L4(2) OR L1(2);
RB1(3) <= L4(3) OR L1(3);
RB1(4) <= L4(4) OR L1(4);
RB1(5) <= L4(5) OR L1(5);
RB1(6) <= L4(6) OR L1(6);
RB1(7) <= L4(7) OR L1(7);
when "00000100" =>
RB2(0) <= L1(0) OR L2(0);
RB2(1) <= L1(1) OR L2(1);
RB2(2) <= L1(2) OR L2(2);
RB2(3) <= L1(3) OR L2(3);
RB2(4) <= L1(4) OR L2(4);
RB2(5) <= L1(5) OR L2(5);
RB2(6) <= L1(6) OR L2(6);
RB2(7) <= L1(7) OR L2(7);
when "00010100" =>
RB2(0) <= L2(0) OR L2(0);
RB2(1) <= L2(1) OR L2(1);
RB2(2) <= L2(2) OR L2(2);
RB2(3) <= L2(3) OR L2(3);
RB2(4) <= L2(4) OR L2(4);
RB2(5) <= L2(5) OR L2(5);
RB2(6) <= L2(6) OR L2(6);
RB2(7) <= L2(7) OR L2(7);
when "00100100" =>
RB2(0) <= L3(0) OR L2(0);
RB2(1) <= L3(1) OR L2(1);
RB2(2) <= L3(2) OR L2(2);
RB2(3) <= L3(3) OR L2(3);
RB2(4) <= L3(4) OR L2(4);
RB2(5) <= L3(5) OR L2(5);
RB2(6) <= L3(6) OR L2(6);
RB2(7) <= L3(7) OR L2(7);
when "00110100" =>
RB2(0) <= L4(0) OR L2(0);
RB2(1) <= L4(1) OR L2(1);
Информация о работе Разработка IP - ядра коммутационного микропроцессора