Автор работы: Пользователь скрыл имя, 01 Декабря 2012 в 20:48, курсовая работа
IP-ядро является блоком логической схемы, которое используется в изготовлении программируемой матрицы логических элементов или специальных интегральных схем. Таким образом, IP-ядро является универсальным элементом при построении интегральных схем. Идеально, IP ядро должно быть полностью переносным – то есть легко устанавливаемым в любую технику. Универсальные асинхронные приемопередатчики, центральные процессоры, регуляторы (контроллеры) Ethernet, и интерфейсы PCI – все примеры ядер IP.
Календарный план
Аннотация
Введение
Техническое задание
Разработка VHDL модели проектируемого устройства
• Граф переходов состояний микропроцессора
• Синтез устройства
• Структурная схема устройства
• Текст программы на языке VHDL
OP_RA1 <= '1';
OP_RA2 <= '1';
OP_RA3 <= '1';
OP_RA4 <= '1';
when "11100001" =>
OP_RA1 <= '1';
OP_RA2 <= '1';
OP_RA3 <= '1';
OP_RA4 <= '1';
when "11100010" =>
OP_RA1 <= '1';
OP_RA2 <= '1';
OP_RA3 <= '1';
OP_RA4 <= '1';
when "11100011" =>
OP_RA1 <= '1';
OP_RA2 <= '1';
OP_RA3 <= '1';
OP_RA4 <= '1';
------------------------------
--------------------
when "11100100" =>
OP_L1 <= '1';
OP_L2 <= '1';
OP_L3 <= '1';
OP_L4 <= '1';
when "11100101" =>
OP_L1 <= '1';
OP_L2 <= '1';
OP_L3 <= '1';
OP_L4 <= '1';
when "11100110" =>
OP_L1 <= '1';
OP_L2 <= '1';
OP_L3 <= '1';
OP_L4 <= '1';
when "11100111" =>
OP_L1 <= '1';
OP_L2 <= '1';
OP_L3 <= '1';
OP_L4 <= '1';
------------------------------
end case;
end process mng_device;
END behavior;
-- VHDL created by OrCAD Express
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.numeric_std.all;
ENTITY logical_device is
PORT (
OP : IN STD_LOGIC_VECTOR (0 TO 7);
RA1signal : IN STD_LOGIC_VECTOR (0 TO 7);
RA2signal : IN STD_LOGIC_VECTOR (0 TO 7);
RA3signal : IN STD_LOGIC_VECTOR (0 TO 7);
RA4signal : IN STD_LOGIC_VECTOR (0 TO 7);
L1 : IN STD_LOGIC_VECTOR (0 TO 7);
L2 : IN STD_LOGIC_VECTOR (0 TO 7);
L3 : IN STD_LOGIC_VECTOR (0 TO 7);
L4 : IN STD_LOGIC_VECTOR (0 TO 7);
Z : OUT STD_LOGIC;
RB1 : OUT STD_LOGIC_VECTOR (0 TO 7);
RB2 : OUT STD_LOGIC_VECTOR (0 TO 7);
RB3 : OUT STD_LOGIC_VECTOR (0 TO 7);
RB4 : OUT STD_LOGIC_VECTOR (0 TO 7));
END logical_device;
ARCHITECTURE behavior OF logical_device IS
--signal T: STD_LOGIC_VECTOR (0 TO 3);
BEGIN
Z <= '0';
logical_device: process(OP,RA1signal,
begin
case OP is
------------------------------
when "00000000" =>
RB1(0) <= RA1signal(0) OR RA1signal(0);
RB1(1) <= RA1signal(1) OR RA1signal(1);
RB1(2) <= RA1signal(2) OR RA1signal(2);
RB1(3) <= RA1signal(3) OR RA1signal(3);
RB1(4) <= RA1signal(4) OR RA1signal(4);
RB1(5) <= RA1signal(5) OR RA1signal(5);
RB1(6) <= RA1signal(6) OR RA1signal(6);
RB1(7) <= RA1signal(7) OR RA1signal(7);
when "00010000" =>
RB1(0) <= RA2signal(0) OR RA1signal(0);
RB1(1) <= RA2signal(1) OR RA1signal(1);
RB1(2) <= RA2signal(2) OR RA1signal(2);
RB1(3) <= RA2signal(3) OR RA1signal(3);
RB1(4) <= RA2signal(4) OR RA1signal(4);
RB1(5) <= RA2signal(5) OR RA1signal(5);
RB1(6) <= RA2signal(6) OR RA1signal(6);
RB1(7) <= RA2signal(7) OR RA1signal(7);
when "00100000" =>
RB1(0) <= RA3signal(0) OR RA1signal(0);
RB1(1) <= RA3signal(1) OR RA1signal(1);
RB1(2) <= RA3signal(2) OR RA1signal(2);
RB1(3) <= RA3signal(3) OR RA1signal(3);
RB1(4) <= RA3signal(4) OR RA1signal(4);
RB1(5) <= RA3signal(5) OR RA1signal(5);
RB1(6) <= RA3signal(6) OR RA1signal(6);
RB1(7) <= RA3signal(7) OR RA1signal(7);
when "00110000" =>
RB1(0) <= RA4signal(0) OR RA1signal(0);
RB1(1) <= RA4signal(1) OR RA1signal(1);
RB1(2) <= RA4signal(2) OR RA1signal(2);
RB1(3) <= RA4signal(3) OR RA1signal(3);
RB1(4) <= RA4signal(4) OR RA1signal(4);
RB1(5) <= RA4signal(5) OR RA1signal(5);
RB1(6) <= RA4signal(6) OR RA1signal(6);
RB1(7) <= RA4signal(7) OR RA1signal(7);
when "00000100" =>
RB2(0) <= RA1signal(0) OR RA2signal(0);
RB2(1) <= RA1signal(1) OR RA2signal(1);
RB2(2) <= RA1signal(2) OR RA2signal(2);
RB2(3) <= RA1signal(3) OR RA2signal(3);
RB2(4) <= RA1signal(4) OR RA2signal(4);
RB2(5) <= RA1signal(5) OR RA2signal(5);
RB2(6) <= RA1signal(6) OR RA2signal(6);
RB2(7) <= RA1signal(7) OR RA2signal(7);
when "00010100" =>
RB2(0) <= RA2signal(0) OR RA2signal(0);
RB2(1) <= RA2signal(1) OR RA2signal(1);
RB2(2) <= RA2signal(2) OR RA2signal(2);
RB2(3) <= RA2signal(3) OR RA2signal(3);
RB2(4) <= RA2signal(4) OR RA2signal(4);
RB2(5) <= RA2signal(5) OR RA2signal(5);
RB2(6) <= RA2signal(6) OR RA2signal(6);
RB2(7) <= RA2signal(7) OR RA2signal(7);
when "00100100" =>
RB2(0) <= RA3signal(0) OR RA2signal(0);
RB2(1) <= RA3signal(1) OR RA2signal(1);
RB2(2) <= RA3signal(2) OR RA2signal(2);
RB2(3) <= RA3signal(3) OR RA2signal(3);
RB2(4) <= RA3signal(4) OR RA2signal(4);
RB2(5) <= RA3signal(5) OR RA2signal(5);
RB2(6) <= RA3signal(6) OR RA2signal(6);
RB2(7) <= RA3signal(7) OR RA2signal(7);
when "00110100" =>
RB2(0) <= RA4signal(0) OR RA2signal(0);
RB2(1) <= RA4signal(1) OR RA2signal(1);
RB2(2) <= RA4signal(2) OR RA2signal(2);
RB2(3) <= RA4signal(3) OR RA2signal(3);
RB2(4) <= RA4signal(4) OR RA2signal(4);
RB2(5) <= RA4signal(5) OR RA2signal(5);
RB2(6) <= RA4signal(6) OR RA2signal(6);
RB2(7) <= RA4signal(7) OR RA2signal(7);
when "00001000" =>
RB3(0) <= RA1signal(0) OR RA3signal(0);
RB3(1) <= RA1signal(1) OR RA3signal(1);
RB3(2) <= RA1signal(2) OR RA3signal(2);
RB3(3) <= RA1signal(3) OR RA3signal(3);
RB3(4) <= RA1signal(4) OR RA3signal(4);
RB3(5) <= RA1signal(5) OR RA3signal(5);
RB3(6) <= RA1signal(6) OR RA3signal(6);
RB3(7) <= RA1signal(7) OR RA3signal(7);
when "00011000" =>
RB3(0) <= RA2signal(0) OR RA3signal(0);
RB3(1) <= RA2signal(1) OR RA3signal(1);
RB3(2) <= RA2signal(2) OR RA3signal(2);
RB3(3) <= RA2signal(3) OR RA3signal(3);
RB3(4) <= RA2signal(4) OR RA3signal(4);
RB3(5) <= RA2signal(5) OR RA3signal(5);
RB3(6) <= RA2signal(6) OR RA3signal(6);
RB3(7) <= RA2signal(7) OR RA3signal(7);
when "00101000" =>
RB3(0) <= RA3signal(0) OR RA3signal(0);
RB3(1) <= RA3signal(1) OR RA3signal(1);
RB3(2) <= RA3signal(2) OR RA3signal(2);
RB3(3) <= RA3signal(3) OR RA3signal(3);
RB3(4) <= RA3signal(4) OR RA3signal(4);
RB3(5) <= RA3signal(5) OR RA3signal(5);
RB3(6) <= RA3signal(6) OR RA3signal(6);
RB3(7) <= RA3signal(7) OR RA3signal(7);
when "00111000" =>
RB3(0) <= RA4signal(0) OR RA3signal(0);
RB3(1) <= RA4signal(1) OR RA3signal(1);
RB3(2) <= RA4signal(2) OR RA3signal(2);
RB3(3) <= RA4signal(3) OR RA3signal(3);
RB3(4) <= RA4signal(4) OR RA3signal(4);
RB3(5) <= RA4signal(5) OR RA3signal(5);
RB3(6) <= RA4signal(6) OR RA3signal(6);
RB3(7) <= RA4signal(7) OR RA3signal(7);
when "00001100" =>
RB4(0) <= RA1signal(0) OR RA4signal(0);
RB4(1) <= RA1signal(1) OR RA4signal(1);
RB4(2) <= RA1signal(2) OR RA4signal(2);
RB4(3) <= RA1signal(3) OR RA4signal(3);
RB4(4) <= RA1signal(4) OR RA4signal(4);
RB4(5) <= RA1signal(5) OR RA4signal(5);
RB4(6) <= RA1signal(6) OR RA4signal(6);
RB4(7) <= RA1signal(7) OR RA4signal(7);
when "00011100" =>
RB4(0) <= RA2signal(0) OR RA4signal(0);
RB4(1) <= RA2signal(1) OR RA4signal(1);
RB4(2) <= RA2signal(2) OR RA4signal(2);
RB4(3) <= RA2signal(3) OR RA4signal(3);
RB4(4) <= RA2signal(4) OR RA4signal(4);
RB4(5) <= RA2signal(5) OR RA4signal(5);
RB4(6) <= RA2signal(6) OR RA4signal(6);
RB4(7) <= RA2signal(7) OR RA4signal(7);
when "00101100" =>
RB4(0) <= RA3signal(0) OR RA4signal(0);
RB4(1) <= RA3signal(1) OR RA4signal(1);
RB4(2) <= RA3signal(2) OR RA4signal(2);
RB4(3) <= RA3signal(3) OR RA4signal(3);
RB4(4) <= RA3signal(4) OR RA4signal(4);
RB4(5) <= RA3signal(5) OR RA4signal(5);
RB4(6) <= RA3signal(6) OR RA4signal(6);
RB4(7) <= RA3signal(7) OR RA4signal(7);
when "00111100" =>
RB4(0) <= RA4signal(0) OR RA4signal(0);
RB4(1) <= RA4signal(1) OR RA4signal(1);
RB4(2) <= RA4signal(2) OR RA4signal(2);
RB4(3) <= RA4signal(3) OR RA4signal(3);
RB4(4) <= RA4signal(4) OR RA4signal(4);
RB4(5) <= RA4signal(5) OR RA4signal(5);
RB4(6) <= RA4signal(6) OR RA4signal(6);
RB4(7) <= RA4signal(7) OR RA4signal(7);
------------------------------
when "00000001" =>
RB1(0) <= RA1signal(0) AND RA1signal(0);
RB1(1) <= RA1signal(1) AND RA1signal(1);
RB1(2) <= RA1signal(2) AND RA1signal(2);
RB1(3) <= RA1signal(3) AND RA1signal(3);
RB1(4) <= RA1signal(4) AND RA1signal(4);
RB1(5) <= RA1signal(5) AND RA1signal(5);
RB1(6) <= RA1signal(6) AND RA1signal(6);
RB1(7) <= RA1signal(7) AND RA1signal(7);
when "00010001" =>
RB1(0) <= RA2signal(0) AND RA1signal(0);
RB1(1) <= RA2signal(1) AND RA1signal(1);
RB1(2) <= RA2signal(2) AND RA1signal(2);
RB1(3) <= RA2signal(3) AND RA1signal(3);
RB1(4) <= RA2signal(4) AND RA1signal(4);
RB1(5) <= RA2signal(5) AND RA1signal(5);
RB1(6) <= RA2signal(6) AND RA1signal(6);
RB1(7) <= RA2signal(7) AND RA1signal(7);
when "00100001" =>
RB1(0) <= RA3signal(0) AND RA1signal(0);
RB1(1) <= RA3signal(1) AND RA1signal(1);
RB1(2) <= RA3signal(2) AND RA1signal(2);
RB1(3) <= RA3signal(3) AND RA1signal(3);
RB1(4) <= RA3signal(4) AND RA1signal(4);
RB1(5) <= RA3signal(5) AND RA1signal(5);
RB1(6) <= RA3signal(6) AND RA1signal(6);
RB1(7) <= RA3signal(7) AND RA1signal(7);
when "00110001" =>
RB1(0) <= RA4signal(0) AND RA1signal(0);
RB1(1) <= RA4signal(1) AND RA1signal(1);
RB1(2) <= RA4signal(2) AND RA1signal(2);
RB1(3) <= RA4signal(3) AND RA1signal(3);
RB1(4) <= RA4signal(4) AND RA1signal(4);
RB1(5) <= RA4signal(5) AND RA1signal(5);
RB1(6) <= RA4signal(6) AND RA1signal(6);
RB1(7) <= RA4signal(7) AND RA1signal(7);
when "00000101" =>
RB2(0) <= RA1signal(0) AND RA2signal(0);
RB2(1) <= RA1signal(1) AND RA2signal(1);
RB2(2) <= RA1signal(2) AND RA2signal(2);
RB2(3) <= RA1signal(3) AND RA2signal(3);
RB2(4) <= RA1signal(4) AND RA2signal(4);
RB2(5) <= RA1signal(5) AND RA2signal(5);
RB2(6) <= RA1signal(6) AND RA2signal(6);
RB2(7) <= RA1signal(7) AND RA2signal(7);
when "00010101" =>
RB2(0) <= RA2signal(0) AND RA2signal(0);
RB2(1) <= RA2signal(1) AND RA2signal(1);
RB2(2) <= RA2signal(2) AND RA2signal(2);
RB2(3) <= RA2signal(3) AND RA2signal(3);
RB2(4) <= RA2signal(4) AND RA2signal(4);
RB2(5) <= RA2signal(5) AND RA2signal(5);
RB2(6) <= RA2signal(6) AND RA2signal(6);
RB2(7) <= RA2signal(7) AND RA2signal(7);
when "00100101" =>
RB2(0) <= RA3signal(0) AND RA2signal(0);
RB2(1) <= RA3signal(1) AND RA2signal(1);
RB2(2) <= RA3signal(2) AND RA2signal(2);
RB2(3) <= RA3signal(3) AND RA2signal(3);
RB2(4) <= RA3signal(4) AND RA2signal(4);
RB2(5) <= RA3signal(5) AND RA2signal(5);
RB2(6) <= RA3signal(6) AND RA2signal(6);
RB2(7) <= RA3signal(7) AND RA2signal(7);
when "00110101" =>
RB2(0) <= RA4signal(0) AND RA2signal(0);
RB2(1) <= RA4signal(1) AND RA2signal(1);
RB2(2) <= RA4signal(2) AND RA2signal(2);
RB2(3) <= RA4signal(3) AND RA2signal(3);
RB2(4) <= RA4signal(4) AND RA2signal(4);
RB2(5) <= RA4signal(5) AND RA2signal(5);
RB2(6) <= RA4signal(6) AND RA2signal(6);
RB2(7) <= RA4signal(7) AND RA2signal(7);
when "00001001" =>
RB3(0) <= RA1signal(0) AND RA3signal(0);
RB3(1) <= RA1signal(1) AND RA3signal(1);
RB3(2) <= RA1signal(2) AND RA3signal(2);
RB3(3) <= RA1signal(3) AND RA3signal(3);
RB3(4) <= RA1signal(4) AND RA3signal(4);
RB3(5) <= RA1signal(5) AND RA3signal(5);
RB3(6) <= RA1signal(6) AND RA3signal(6);
RB3(7) <= RA1signal(7) AND RA3signal(7);
when "00011001" =>
RB3(0) <= RA2signal(0) AND RA3signal(0);
RB3(1) <= RA2signal(1) AND RA3signal(1);
RB3(2) <= RA2signal(2) AND RA3signal(2);
RB3(3) <= RA2signal(3) AND RA3signal(3);
RB3(4) <= RA2signal(4) AND RA3signal(4);
RB3(5) <= RA2signal(5) AND RA3signal(5);
RB3(6) <= RA2signal(6) AND RA3signal(6);
RB3(7) <= RA2signal(7) AND RA3signal(7);
when "00101001" =>
RB3(0) <= RA3signal(0) AND RA3signal(0);
Информация о работе Разработка IP - ядра коммутационного микропроцессора